The present invention concerns a unit for switching data transmitted by asynchronous time-division multiplexing known as an ATD (Asynchronous Time Division) switching matrix. In this context the term "data" is to be understood in its widest sense encompassing information comprising speech, pictures and all kinds of data in the usual sense to be transmitted and switched through the integrated services digital network (ISDN).
In asynchronous time-division (ATD) transmission as understood in this context the transmission medium of a transmission link is temporally divided into equal intervals each conveying one cell, meaning a group comprising a specific number of binary information units or bits, including a label containing a destination indication and a data field containing the communication information proper. The data rates of the tranmission link in current projects is in the order of several 100 megabits per second.
Switching consists of receiving digital information structured in this way from several input links and retransmitting the information on several output links. To be more precise, a cell received on one of the input links is retransmitted on one of the output links as designated by the destination indication contained in the cell.
A switching unit is a unitary device implementing switching of this kind between a defined number of input links and a defined number of output links. Switching units of this kind may be combined into a multistage switching network. In this case the destination indication must meet the requirements of each of the switching units passed through.
At a switching unit and in a stationary switching state the cells from one input link intended for the same output link constitute a data stream the average data rate of which is constant but the instantaneous data rate of which is subject to fluctuations that may be regarded as random. The cells retransmitted on an output link originate from several input links and represent the addition of several independent streams. The network control means must be such that the average data rate corresponding to this addition is at most equal to the transmission capacity of the output link if congestion is to be avoided. For reasons of efficiency, however, this average total data rate must also be able to approach as closely as possible the nominal transmission capacity of the link. This means that the sum of the instantaneous data rates will from time to time exceed the transmission capacity of the output link. Outside these peak periods this capacity will not be fully utilized.
Within a switching unit the foregoing considerations lead to the provision of a buffer memory receiving the cells from the input links and storing them until they can be retransmitted on the output links.
A switching unit meeting the requirement as just defined is the subject of the French Pat. No. 2 538 976. This describes a switching unit for data transmitted by ATD multiplexing comprising receive circuits each associated with an input link and supplying cells received by that input link, transmit circuits each associated with an output link and sending retransmitted cells on that output link, a buffer memory storing received cells supplied by the receive circuits and delivering cells to be retransmitted to the transmit circuits, and a buffer memory addressing device including a write address source and a read address source.
The received cells appear on a bus leading to the buffer memory into which the received cells from the various input links are written cyclically. In parallel with this the label of each cell is analyzed by means of a control memory and supplies the address of the output link for which the cell is intended. This address designates a "first in-first out" (FIFO) memory associated with the output link. It makes it possible to write into the latter the address of the buffer memory location in which the cell in question has been written. The output FIFO memory of each output link therefore indicates where the cells to be retransmitted on that output link are to be read out from the buffer memory.
The buffer memory is addressed in a cyclical way, as explained above, to write into it the received cells on the input links of the switching unit; a timebase supplies the addresses of the write locations in the buffer memory one after the other and the cells arriving in succession on the input links are written in order into those locations. It is just as if the buffer memory were subdivided into as many memory parts as there are input links. The number of memory locations in each part is the same for all the input links. Given the conditions as explained hereinabove, this number must be such as to meet the writing requirements specific to the most heavily loaded input links.